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1. general description the 74lvt573 is a high-performance bicmos product designed for v cc operation at 3.3 v. this device is an octal transparent latch coupled to eight 3-state output buffers. the two sections of the device are controlled inde pendently by latch enable (le) and output enable (oe ) control gates. the 74lvt573 has a broadside pinout configuration to facilitate pc board layout and allow easy interface with microprocessors. the data on the dn inputs are transferred to the latch outputs when the latch enable (le) input is high. the latch remains transparent to the data inputs while le is high, and stores the data that is present one setup time before the high-to-low enable transition. the 3-state output buffers are designed to drive heavily loaded 3-state buses, mos memories, or mos microprocessors. the active-low output enable (oe ) controls all eight 3-state buffers independent of the latch operation. when oe is low, the latched or transparent data appears at the outputs. when oe is high, the outputs are in the high-impedance ?off? state, wh ich means they will neither drive nor load the bus. 2. features and benefits ? inputs and outputs arranged for easy interfacing to microprocessors ? 3-state outputs for bus interfacing ? common output enable control ? ttl input and output switching levels ? input and output interface capa bility to systems at 5 v supply ? bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs ? live insertion and extraction permitted ? no bus current loading when output is tied to 5 v bus ? power-up reset ? power-up 3-state ? latch-up protection ? jesd78 class ii exceeds 500 ma ? esd protection: ? hbm jesd22-a114e exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v ? specified from ? 40 ? c to +85 ? c 74lvt573 3.3 v octal d-type transparent latch; 3-state rev. 8 ? 22 november 2011 product data sheet
74lvt573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 8 ? 22 november 2011 2 of 17 nxp semiconductors 74lvt573 3.3 v octal d-type transparent latch; 3-state 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74lvt573d ? 40 ? c to +85 ? c so20 plastic small outline package; 20 leads; body width 7.5 mm sot163-1 74lvt573db ? 40 ? c to +85 ? c ssop20 plastic shrink small outline package; 20 leads; body width 5.3 mm sot339-1 74lvt573pw ? 40 ? c to +85 ? c tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 74LVT573BQ ? 40 ? cto+85? c dhvqfn20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 ? 4.5 ? 0.85 mm sot764-1 fig 1. logic symbol fig 2. iec logic symbol mna807 d0 d1 d2 d3 d4 d5 d6 d7 le oe q0 q1 q2 q3 q4 q5 q6 q7 1 11 12 13 14 15 16 17 18 19 9 8 7 6 5 4 3 2 mna808 12 13 14 15 16 17 18 11 c1 1 en1 1d 19 9 8 7 6 5 4 3 2
74lvt573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 8 ? 22 november 2011 3 of 17 nxp semiconductors 74lvt573 3.3 v octal d-type transparent latch; 3-state 5. pinning information 5.1 pinning fig 3. logic diagram mna810 q4 d4 d le q q3 d3 d le q q2 d2 d le q q1 d1 d le lele q q0 d0 d latch 1 latch 2 latch 3 latch 4 latch 5 q le oe le le le le q5 d5 d le q latch 6 le q6 d6 d le q latch 7 le q7 d7 d le q latch 8 le (1) the die substrate is attached to this pad using conductive die attach materi al. it can not be used as a supply pin or input. fig 4. pin configuration for so20 and (t)ssop20 fig 5. pin configuration for dhvqfn20 74lvt573 oe v cc d0 q0 d1 q1 d2 q2 d3 q3 d4 q4 d5 q5 d6 q6 d7 q7 gnd le 001aah713 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 001aah712 74lvt573 transparent top view q7 d6 d7 q6 d5 q5 d4 q4 d3 q3 d2 q2 gnd (1) d1 q1 d0 q0 gnd le oe v cc 9 12 8 13 7 14 6 15 5 16 4 17 3 18 2 19 10 11 1 20 terminal 1 index area
74lvt573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 8 ? 22 november 2011 4 of 17 nxp semiconductors 74lvt573 3.3 v octal d-type transparent latch; 3-state 5.2 pin description 6. functional description 6.1 function table [1] h = high voltage level; l = low voltage level; ? = high-to-low latch enable transition; h = high voltage level one setup time prior to the low-to-high clock transition; l = low voltage level one setup time prior to the low-to-high clock transition; z = high-impedance off-state; nc = no change; x = don?t care. 7. limiting values table 2. pin description symbol pin description oe 1 output enable input (active low) d0 to d7 2, 3, 4, 5, 6, 7, 8, 9 data input gnd 10 ground (0 v) le 11 latch enable (active high) q0 to q7 19, 18, 17, 16, 15, 14, 13, 12 data output v cc 20 supply voltage table 3. function table [1] operating mode control oe control le input dn internal register output qn load and read register enable lhlll hhh latch and read register l ? lll hhh hold l l x nc nc disable outputs h l x nc z hdndnz table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +4.6 v v i input voltage [1] ? 0.5 +7.0 v v o output voltage output in off-state or high-state [1] ? 0.5 +7.0 v i ik input clamping current v i <0v - ? 50 ma i ok output clamping current v o <0v - ? 50 ma i o output current output in low-state - 128 ma output in high-state - ? 64 ma
74lvt573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 8 ? 22 november 2011 5 of 17 nxp semiconductors 74lvt573 3.3 v octal d-type transparent latch; 3-state [1] the input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] the performance capability of a high-perfo rmance integrated circuit in conjunction with its thermal environment can create j unction temperatures which are detrimental to reliability. [3] for so20 packages: above 70 ? c derate linearly with 8 mw/k. for ssop20 and tssop20 packages: above 60 ? c derate linearly with 5.5 mw/k. for dhvqfn20 packages: above 60 ? c derate linearly with 4.5 mw/k. 8. recommended operating conditions 9. static characteristics t stg storage temperature ? 65 +150 ?c t j junction temperature [2] - 150 ?c p tot total power dissipation t amb = ? 40 ? c to +85 ?c [3] - 500 mw table 4. limiting values ?continued in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit table 5. recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage 2.7 - 3.6 v v i input voltage 0 - 5.5 v v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v i oh high-level output current - - ? 32 ma i ol low-level output current - - 32 ma current duty cycle ? 50 %; f i ? 1khz--64ma t amb ambient temperature in free air ? 40 - +85 ?c ? t/ ? v input transition rise and fall rate outputs enabled - - 10 ns/v table 6. static characteristics at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions t amb = ? 40 ?c to +85 ?c unit min typ [1] max v ik input clamping voltage v cc = 2.7 v; i ik = ? 18 ma ? 1.2 ? 0.9 - v v oh high-level output voltage v cc = 2.7 v to 3.6 v; i oh = ? 100 ? a v cc ? 0.2 v cc ? 0.1 - v v cc = 2.7 v; i oh = ? 8ma 2.4 2.5 - v v cc = 3.0 v; i oh = ? 32 ma 2.0 2.2 - v v ol low-level output voltage v cc = 2.7 v; i ol =100 ? a-0.10.2v v cc = 2.7 v; i ol =24ma - 0.3 0.5 v v cc = 3.0 v i ol = 16 ma - 0.25 0.4 v v cc = 3.0 v i ol =32ma - 0.3 0.5 v v cc = 3.0 v i ol =64ma - 0.4 0.55 v v ol(pu) power-up low-level output voltage v cc = 3.6 v; i o =1ma; v i =gndorv cc [2] - 0.13 0.55 v
74lvt573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 8 ? 22 november 2011 6 of 17 nxp semiconductors 74lvt573 3.3 v octal d-type transparent latch; 3-state [1] typical values are measured at v cc = 3.3 v and t amb = 25 ? c. [2] for valid test results, data must not be loaded into the flip-flops (or latches) after applying power. [3] unused pins at v cc or gnd. [4] this is the bus hold overdrive current requir ed to force the input to the opposite logic state. [5] this parameter is valid for any v cc between 0 v and 1.2 v with a transition time of up to 10 ms. from v cc = 1.2 v to v cc =3.3 v ? 0.3 v a transition time of 100 ? s is permitted. this parameter is valid for t amb =25 ? c only. [6] i cc is measured with outputs pulled to v cc or gnd. [7] this is the increase in supply current for each input at the specified voltage level other than v cc or gnd. i i input leakage current all input pins; v cc = 0 v or 3.6 v; v i =5.5v - 1 10 ? a control pins; v cc = 3.6 v; v cc or gnd - ? 0.1 ? 1 ? a data pins v cc = 3.6 v; v i =v cc [3] -0.11 ? a v cc = 3.6 v; v i =0v ? 5 ? 1- ? a i off power-off leakage current v cc = 0 v; v i or v o = 0 v to 4.5 v - 1 ? 100 ? a i bhl bus hold low current dn input; v cc = 3 v; v i =0.8v [4] 75 150 - ? a i bhh bus hold high current dn input; v cc = 3 v; v i =2.0v - ? 150 ? 75 ? a i bhho bus hold high overdrive current dn input; v cc = 3.6; v i = 0 v to 3.6 v [4] --500 ? a i bhlo bus hold low overdrive current dn input; v cc = 3.6; v i = 0 v to 3.6 v ? 500 - - ? a i lo output leakage current qn output high when v o = 5.5 v and v cc =3.0v -60125 ? a i o(pu/pd) power-up/power-down output current v cc ? 1.2 v; v o =0.5vto v cc ; v i =gndorv cc ; oe = don?t care [5] -1 ? 100 ? a i oz off-state output current v cc = 3.6 v; v i =v ih or v il output high: v o =3.0v - 1 5 ? a output low: v o =0.5v ? 5 ? 1- ? a i cc supply current v cc = 3.6 v; v i =gndorv cc ; i o =0a outputs high - 0.13 0.19 ma outputs low - 3 12 ma outputs disabled [6] - 0.13 0.19 ma ? i cc additional supply current per input pin; v cc = 3 v to 3.6 v; one input at v cc ? 0.6 v and other inputs at v cc or gnd [7] -0.10.2ma c i input capacitance v i = 0 v or 3.0 v - 4 - pf c o output capacitance outputs disabled; v o = 0 v or 3.0 v - 8 - pf table 6. static characteristics ?continued at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions t amb = ? 40 ?c to +85 ?c unit min typ [1] max
74lvt573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 8 ? 22 november 2011 7 of 17 nxp semiconductors 74lvt573 3.3 v octal d-type transparent latch; 3-state 10. dynamic characteristics [1] typical values are at v cc = 3.3 v and t amb =25 ? c. [2] t su is the same as t su(l) and t su(h) . [3] t h is the same as t h(l) and t h(h) . [4] t w is the same as t wl and t wh . table 7. dynamic characteristics voltages are referenced to ground (gnd = 0 v); for test circuit see figure 11 . symbol parameter conditions t amb = ? 40 ? c to +85 ?c unit min typ [1] max t plh low to high propagation delay le to qn; see figure 6 v cc = 3.0 v to 3.6 v 1.6 3.5 5.6 ns v cc = 2.7 v - - 6.3 ns dn to qn; see figure 7 v cc = 3.0 v to 3.6 v 1.0 2.5 4.2 ns v cc = 2.7 v - - 4.7 ns t phl high to low propagation delay le to qn; see figure 6 v cc = 3.0 v to 3.6 v 2.5 4.3 6.5 ns v cc = 2.7 v - - 7.2 ns dn to qn; see figure 7 v cc = 3.0 v to 3.6 v 1.0 2.7 4.3 ns v cc = 2.7 v - - 5.2 ns t pzh off-state to high propagation delay oe to qn; see figure 8 v cc = 3.0 v to 3.6 v 1.0 2.8 5.1 ns v cc = 2.7 v - - 6.2 ns t pzl off-state to low propagation delay oe to qn; see figure 9 v cc = 3.0 v to 3.6 v 1.3 3.3 5.5 ns v cc = 2.7 v - - 6.6 ns t phz high to off-state propagation delay oe to qn; see figure 8 v cc = 3.0 v to 3.6 v 2.0 3.7 5.7 ns v cc = 2.7 v - - 6.7 ns t plz low to off-state propagation delay oe to qn; see figure 9 v cc = 3.0 v to 3.6 v 1.5 3.0 4.6 ns v cc = 2.7 v - - 5.1 ns t su set-up time dn to le; see figure 10 [2] v cc = 3.0 v to 3.6 v 0.7 - - ns v cc =2.7v 0.6 - - ns t h hold time dn to le; see figure 10 [3] v cc = 3.0 v to 3.6 v 1.6 - - ns v cc =2.7v 1.8 - - ns t w pulse width le input high; see figure 6 [4] v cc = 3.0 v to 3.6 v 3.3 - - ns v cc =2.7v 3.3 - - ns
74lvt573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 8 ? 22 november 2011 8 of 17 nxp semiconductors 74lvt573 3.3 v octal d-type transparent latch; 3-state 11. waveforms measurement points are given in table 8 . measurement points are given in table 8 . fig 6. propagation delays latch enable input (le) to output (qn), and latch enable (le) pulse width fig 7. propagation delay data input (dn) to output (qn) measurement points are given in table 8 . v ol and v oh are typical voltage output levels that occur with the output load. measurement points are given in table 8 . fig 8. output enable time to high-state and output disable time from high-state fig 9. output enable time to low-state and output disable time from low-state measurement points are given in table 8 . remark: the shaded areas indicate when the input is permitt ed to change for predictable output performance. fig 10. data setup and hold times for data (dn) and latch enable (le) inputs 001aai743 le input qn output t phl t plh t wh v m v oh v i 0 v v ol v m t wl 001aai742 dn input qn output t phl t plh 0 v v i v m v m v oh v ol qn output 001aai745 oe input v m v i v oh 0 v 0 v t pzh t phz v y v m v m 001aai746 t pzl t plz v m v m v m qn output oe input v i v ol 3.0 v v x 0 v 001aai744 t h(l) t su(l) t h(h) t su(h) v m v m v i 0 v v i 0 v le input dn input table 8. measurement points input output v m v m v x v y 1.5v 1.5v v ol + 0.3 v v oh ? 0.3 v
74lvt573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 8 ? 22 november 2011 9 of 17 nxp semiconductors 74lvt573 3.3 v octal d-type transparent latch; 3-state test data is given in table 9 . definitions test circuit: r l = load resistance. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to output impedance z o of the pulse generator. v ext = test voltage for switching times. fig 11. test circuitry for switching times v ext v cc v i v o 001aae235 dut c l r t r l r l pulse generator v m v m t w t w 10 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % t f t r t r t f table 9. test data input load v ext v i f i t w t r , t f c l r l t phz , t pzh t plz , t pzl t plh , t phl 2.7 v ? 10 mhz 500 ns ? 2.5 ns 50 pf 500 ? gnd 6 v open
74lvt573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 8 ? 22 november 2011 10 of 17 nxp semiconductors 74lvt573 3.3 v octal d-type transparent latch; 3-state 12. package outline fig 12. package outline sot163-1 (so20) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z ywv references outline version european projection issue date iec jedec jeita mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot163-1 10 20 w m b p detail x z e 11 1 d y 0.25 075e04 ms-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale x a a 1 a 2 h e l p q e c l v m a (a ) 3 a so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1 99-12-27 03-02-19
74lvt573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 8 ? 22 november 2011 11 of 17 nxp semiconductors 74lvt573 3.3 v octal d-type transparent latch; 3-state fig 13. package outline sot339-1 (ssop20) unit a 1 a 2 a 3 b p cd (1) e (1) eh e ll p q (1) zywv references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 0.9 0.7 0.9 0.5 8 0 o o 0.13 1.25 0.2 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.2 mm maximum per side are not included. 1.03 0.63 sot339-1 mo-150 99-12-27 03-02-19 x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 11 0 20 11 y 0.25 pin 1 index 0 2.5 5 mm scale ssop20: plastic shrink small outline package; 20 leads; body width 5.3 mm sot339-1 a max. 2
74lvt573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 8 ? 22 november 2011 12 of 17 nxp semiconductors 74lvt573 3.3 v octal d-type transparent latch; 3-state fig 14. package outline sot360-1 (tssop20) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot360-1 mo-153 99-12-27 03-02-19 w m b p d z e 0.25 11 0 20 11 pin 1 index a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 a max. 1.1
74lvt573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 8 ? 22 november 2011 13 of 17 nxp semiconductors 74lvt573 3.3 v octal d-type transparent latch; 3-state fig 15. package outline sot764-1 (dhvqfn20) terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 4.6 4.4 d h 3.15 2.85 y 1 2.6 2.4 1.15 0.85 e 1 3.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot764-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot764-1 dhvqfn20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 29 19 12 11 10 1 20 x d e c b a terminal 1 index area ac c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) 02-10-17 03-01-27
74lvt573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 8 ? 22 november 2011 14 of 17 nxp semiconductors 74lvt573 3.3 v octal d-type transparent latch; 3-state 13. abbreviations 14. revision history table 10. abbreviations acronym description bicmos bipolar complementary metal oxide semiconductor dut device under test esd electrostatic discharge hbm human body model mm machine model ttl transistor-transistor logic table 11. revision history document id release date data sheet status change notice supersedes 74lvt573 v.8 20111122 product data sheet - 74lvt573 v.7 modifications: ? legal pages updated. 74lvt573 v.7 20110912 product data sheet - 74lvt573 v.6 74lvt573 v.6 20110727 product data sheet - 74lvt573 v.5 74lvt573 v.5 20110629 product data sheet - 74lvt573 v.4 74lvt573 v.4 20080915 product data sheet - 74lvt573 v.3 74lvt573 v.3 20011217 product data sheet - 74lvt573 v.2 74lvt573 v.2 19980219 product specification - -
74lvt573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 8 ? 22 november 2011 15 of 17 nxp semiconductors 74lvt573 3.3 v octal d-type transparent latch; 3-state 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? 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stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from competent authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
74lvt573 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 8 ? 22 november 2011 16 of 17 nxp semiconductors 74lvt573 3.3 v octal d-type transparent latch; 3-state non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74lvt573 3.3 v octal d-type transparent latch; 3-state ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 22 november 2011 document identifier: 74lvt573 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 functional description . . . . . . . . . . . . . . . . . . . 4 6.1 function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 recommended operating conditions. . . . . . . . 5 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 5 10 dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 15 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 contact information. . . . . . . . . . . . . . . . . . . . . 16 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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